Principal Engineer – ASIC Validation

Infinera Corp.

San Jose, CA


CA Pay Range (Annual):

$156,800.00 - $291,200.00

Non-CA Pay Range (Annual):

$141,100.00 - $262,100.00

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.

Infinera also offers paid leave, medical,

dental, and vision coverage, 401(k), ESPP,

life, and disability insurance and to

eligible employees.

Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop, and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine networks. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world’s largest and most demanding networks that generate billions in service revenue for our customers.

In this role, you will be responsible for post-silicon validation of ASIC/FPGA including defining & development of suitable validation environment. Your expertise in managing the technical aspects and adhering to project timeline will be much desired. You will have the full ownership for technical quality and timely completion of a project.

What you will be doing:

· Work closely with peers in architecture, design, verification, emulation, SDK, Hardware teams and project team members

· Define validation test plan and traceability to ASIC/FPGA feature set

· Participate in evaluation board requirement & design specification

· Define APIs to enable x-functional & MFG testing of the ASIC

· Estimate the scope of work & evaluate risks

· Own the execution of the project

· Provide crisp and timely summary status and issues for escalation

· Provide leadership and mentor a team of talented Engineers

What we seek:

· Experience: 8+ yrs with MS & 12+ yrs with BS

· Prior experience with successful post-silicon validation

· Ability to triage silicon issues and defining suitable workaround

· Ability to review the arch, requirements and micro-arch details

· Good communication, interpersonal skills.

· Ability to mentor and bring together engineers with differing but valid technical viewpoints

· Explore new methodologies to improve quality of post-silicon validation such that any issue is identified before system integration

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Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.

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