Analog IC Design Engineer, Senior Staff
Cavium Networks, Inc.
Santa Clara, CA
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your ImpactCE AMS ACE PHY group supports analog mixed signal product development for Automotive and Ethernet PHY businesses in Marvell.
What You Can Expect
You will be working with multi-functional teams to deliver high-speed Ethernet products. You will define specifications based on link budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally, with the team, you will drive designs into volume production and delight customers.
What We're Looking For
Master’s degree and/or PhD in Electrical Engineering and 3+ years of experience.
* The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers.
* Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, filters
* In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
* Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:
* Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE
* Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.)
* Familiarity with CDR architectures and implementations
* Design experience in advanced CMOS technologies, design with FinFet technology
* Experience in lab testing of high-speed transceivers
* Modeling of passive on-chip elements such as inductor, T-coil, and transformer
* Able to build VerilogA/AMS behavioral models
* Able to analyze and lead characterization data from lab and volume testing
* Knowledge of ESD requirements
Expected Base Pay Range (USD)128,160 - 192,000, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.ID:uDnQdo