onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. 

onsemi is recognized as one of the world’s most ethical companies and our Core Values of respect, integrity and initiative are on display each day. You’ll have an opportunity to join a diverse, talented and global Central IP engineering team that focuses on development of IP for reuse across the entire company.  The focus of this position will be to architect, design, and analyze custom memory IP to be used in onsemi products.  As a key member of the design team, it will be your responsibility to work directly with your management, our internal customers, and your peers in the Central IP organization to deliver high quality, on time, and on budget memory IP as committed during the Plan Phase. 

Core Responsibilities 

Responsibility for Architecting and Developing custom Memory IP for onsemi products as key member of the Central IP organization 

• Architect, design and build memories and memory sub-systems at the gate and transistor level 
  
• Create test benches, simulate, and analyze the results of your designs 
  
• Perform parasitic extraction and post-layout simulations and analyze results
• Work closely with the organization’s layout team to optimize area and performance of memory leaf cell designs you create 
  
• Floorplan the physical design and leaf cell layout integration required to complete the macro 
  
• Create design specifications and datasheets used by consumers of the memory IP 
  
• Work closely with the IP Automation team who will turn your designs into memory compilers used by our internal customers 
  
• Work directly with the validation and qualification teams to help specify test chips and test plans for all post silicon activities 

Technical Qualifications & Skills

• Minimum BS/MS in Electrical Engineering or related technical field 
  
• 10+ years SRAM and ROM design experience  
  
• Solid understanding of semiconductor device physics  
  
• Demonstrable experience with liberty timing views and Verilog RTL 
  
• Expert level understanding of variation analysis and design margining required to produce high yielding circuits 
  
• Proficiency in running simulations, scripting and is up to date on most commonly used design tools 
  
• Good, working level understanding of EM/IR Analysis, DFT and DFM methodologies 
  
• Solid communication, presentation and interpersonal skills 
  
• Design experience with floating gate NVM and OTP design a plus 

#LI- DS1

ID:uDnQdo