Sr High Speed Mixed Signal Circuit Design Engineer

Infinera Corp.

San Jose, CA

Infinera is a global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine network. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world’s largest and most demanding networks that generate billions in service revenue for our customers.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry.

Essential Functions and Key Responsibilities:

  • Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
  • Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
  • Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
  • Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
  • Need to support and comply with the team’s design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities:

  • Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
  • Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
  • Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
  • Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
  • Must have a good understanding of device physics and the impacts of layout effects;
  • Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
  • Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

  • Fluent in verbal and written communications;
  • Independently resolves issues and conquer design challenges;
  • Self-motivated and detail-oriented;
  • Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

  • Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.

Please note that Infinera has adopted a mandatory COVID-19 vaccination policy to safeguard the health and well-being of our employees. As a condition of employment, our employees are required to be fully vaccinated for COVID-19, unless a reasonable accommodation for a medical/disability or religious basis is approved or as otherwise required by law. Candidates are not required to and must not furnish proof of vaccination or request an accommodation during the application process. Candidates will be required to do so only after a job offer has been extended and prior to their start date if they accept the job offer. A person is fully vaccinated against COVID-19 if the person has received one dose of the Johnson & Johnson COVID-19 vaccine or two doses of the Pfizer or Moderna vaccine and two weeks have passed since receiving the final dose of the vaccine.


Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.